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nonreflective, silicon sp4t switch, 0.1 ghz to 6.0 ghz data sheet HMC7992 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical support www.analog.com features nonreflective, 50 design high isolation: 45 db typical at 2 ghz low insertion loss: 0.6 db at 2 ghz high power handling 33 dbm through path 27 dbm terminated path high linearity 1 db compression (p1db): 35 dbm typical input third-order intercept (iip3): 58 dbm typical esd rating: 2 kv human body model (hbm), class 2 single positive supply: 3.3 v to 5.0 v standard ttl-, cmos-, and 1.8 v-compatible control 16-lead, 3 mm 3 mm lfcsp package (9 mm 2 ) pin compatible with the hmc241alp3e applications cellular/4g infrastructure wireless infrastructure automotive telematics mobile radios test equipment functional block diagram gnd rfc gnd gnd gnd v dd ba rf1 gnd gnd rf2 rf4 gnd gnd rf3 16 15 14 13 11 10 2 3 5678 2:4 ttl decoder package base gnd 12 9 1 4 13714-001 HMC7992 figure 1. general description the HMC7992 is a general-purpose, nonreflective, 0.1 ghz to 6.0 ghz, silicon, single-pole, four-throw (sp4t) switch in a leadless, surface-mount package. the switch is ideal for cellular infrastructure applications, offers high isolation of 45 db typical at 2 ghz, and a low insertion loss of 0.6 db at 2 ghz. it offers excellent power handling capability up to 6.0 ghz, with input power of 1 db compression point (p1db) of 35 dbm at 5 v operation. the HMC7992 has good low frequency input power handling below 0.1 ghz and can operate well down to 10 khz, with a typical 1 db compression of 21 dbm (see figure 21) and an iip3 of 37 dbm (see figure 22) at 1 mhz. the on-chip circuitry allows the HMC7992 to operate at a single, positive supply voltage range from 3.3 v to 5 v, and as well as a single, positive control voltage from 0 v to 1.8 v/3.3 v/5.0 v. a 2:4 decoder integrated in the switch requires only two controlled input signals, with a positive control voltage range from 0 v to 1.8 v/3.3 v/5.0 v, to select one of the four radio frequency (rf) paths.
HMC7992 data sheet rev. 0 | page 2 of 13 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 gene ral description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 digital control voltages .............................................................. 4 bias and supply current .............................................................. 4 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 interface schematics ..................................................................... 6 typi cal performance characteristics ..............................................7 insertion loss, isolation, and return loss ................................7 input compression and input third - order intercept (0.1 ghz to 6.0 ghz) ....................................................................9 input compression and input third - order intercept (10 khz to 1 ghz) ..................................................................................... 10 theory of operation ...................................................................... 11 applications information .............................................................. 12 outline dimensions ....................................................................... 13 ordering guide .......................................................................... 13 revision history 1/1 6r evision 0: initial version
data sheet HMC7992 rev. 0 | page 3 of 13 specifications v dd = 3.3 v to 5.0 v, v ctl = 0 v/v dd , t a = 25c, 50 ? system, unless otherwise noted. table 1 . parameter symbol test conditions/comments min typ max unit insertion loss 0.1 ghz to 2.0 ghz 0.6 0.9 db 2.0 ghz to 4.0 ghz 0.7 1.1 db 4.0 ghz to 6.0 ghz 1.0 1.5 db isolation rfc to rf1to rf4 (worst case) 0.1 ghz to 2.0 ghz 40 45 db 2.0 ghz to 4.0 ghz 32 37 db 4.0 ghz to 6.0 ghz 25 30 db return loss on state 0.1 ghz to 2.0 ghz 25 db 2.0 ghz to 4.0 ghz 24 db 4.0 ghz to 6.0 ghz 17 db off state 0.1 ghz to 2.0 ghz 7 db 0.4 ghz to 1.0 ghz 15 db 1.0 ghz to 6.0 ghz 20 db switching speed rise time and fall time t rise , t fal l 30 ns on time and off time t on , t off 10%/90% rf out 150 ns radio frequency (rf) settling time 50% v ctl to 0.1 db margin of final rf out 320 ns input power 0.1 ghz to 6.0 ghz 1 db compression p1db v dd = 5 v 35 db v dd = 3.3 v 33 db 0.1 db compression p0.1db v dd = 5 v 33 db v dd = 3.3 v 31 db input third - order intercept i ip3 0.1 ghz to 6.0 ghz, two - tone input power = 14 dbm/tone v dd = 5 v 58 dbm v dd = 3.3 v 56 dbm recommended operating conditions bias voltage range v dd 3.0 5.4 v control voltage range v ctl 0 v dd v case temperature range t case ?40 +105 c maximum rf input power 0.1 ghz to 6.0 ghz through path v dd /v ctl = 5 v, t case = 105c 30 dbm v dd /v ctl = 5 v, t case = ?40c to +85c 33 dbm v dd /v ctl = 3.3 v, t case = 105c 29 dbm v dd /v ctl = 3.3 v, t case = ?40c to +85c 32 dbm terminated path v dd /v ctl = 3.3 v to 5 v, t case = 105c 21 dbm v dd /v ctl = 3.3 v to 5 v, t case = 85c 24 dbm v dd /v ctl = 3.3 v to 5 v, t case = 25c 27 dbm v dd /v ctl = 3.3 v to 5 v, t case = ?40c 27 dbm hot switching v dd /v ctl = 3.3 v to 5 v, t case = 105c 24 dbm v dd /v ctl = 3.3 v to 5 v, t case = ?40c to +85c 27 dbm
HMC7992 data sheet rev. 0 | page 4 of 13 digital control volt ages t case = ?40c to +105c, unless otherwise specified. table 2 . parameter symbol min typ max unit test conditions/comments input control voltage <1 a typical low voltage v il 0 8.5 v v dd = 3.3 v (5% v dd ) 0 1.2 v v dd = 5 v (5% v dd ) high voltage v ih 1.15 3.3 v v dd = 3.3 v (5% v dd ) 1.55 5.0 v v dd = 5 v (5% v dd ) bias and supply curr ent table 3 . parameter symbol min typ max unit supply current i dd v dd = 3.3 v 0.1 6 0. 20 ma v dd = 5 v 0.1 8 0.2 3 ma
data sheet HMC7992 rev. 0 | page 5 of 13 absolute maximum rat ings table 4 . parameter rating bias voltage range (v dd ) ?0.3 v to +5.5 v control voltage range (a, b) ?0.5 v to v dd + (+0.5 v) rf input power, 1 3.3 v to 5 v (see figure 2 and figure 3 ) through path 34 dbm terminated path 28 dbm hot switching 30 dbm channel temperature 135c storage temperature range ?65c to +150c maximum peak reflow t emperature (msl3) 260c thermal resistance (channel to package bottom) through path 115c terminated path 200c esd sensitivity human body model ( hbm ) 2 kv (class 2) charged device model ( cdm ) 1.25 kv 1 for recommended operating conditions, see table 1 . stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or a ny other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. 36 34 32 30 28 26 24 0.1 1 frequenc y (ghz) 10 maximum rf input power (dbm) through amr termin a ted amr 13714-002 figure 2. maximum rf input power vs. frequency 35 29 power der a ting (dbm) 31 33 27 25 23 21 19 0.1 1 frequenc y (ghz) 10 through ( a t 8 5 c) through ( a t 10 5 c) termin a ted ( a t 8 5 c) termin a ted ( a t 10 5 c) 13714-003 figure 3. power derating vs. frequency esd caution
HMC7992 data sheet rev. 0 | page 6 of 13 pin configuration an d function descripti ons 12 1 1 10 1 3 4 9 2 6 5 7 8 16 15 14 13 notes 1. the exposed p ad must connect t o rf/dc ground. rf4 gnd gnd rf3 rf1 gnd gnd rfc gnd gnd gnd rf2 gnd v dd b a HMC7992 t o p view (not to scale) 13714-004 figure 4. pin configuration table 5 . pin function descriptions pin no. mnemonic description 1 rf4 rf port 4. this pin is dc - coupled and matched to 50 ?. a dc blocking capacitor is required on this pin. 2, 3, 5, 10, 11, 13, 14, 16 gnd ground. the package bottom has an exposed metal pad that must connect to the printed circuit board (pcb) rf /dc ground. see figure 5 for the gnd interface schematic. 4 rf3 rf port 3. this pin is dc - coupled and matched to 50 ?. a dc blocking capacitor is required on this pin. 6 v dd supply voltage. 7 b logic control inp ut b . see figure 6 for the control input interface schematic. see table 6 and the recommended input control voltages range in table 2 . 8 a logic control input a . see figure 6 for the control input interface schematic. see table 6 and the recommended input control voltages range in table 2 . 9 rf2 rf port 2. this p in is dc - coupled and matched to 50 ?. a dc blocking capacitor is required on this pin. 12 rf1 rf port 1. this pin is dc - coupled and matched to 50 ?. a dc blocking capacitor is required on this pin. 15 rfc rf common port. this pin is dc - coupled and matche d to 50 ?. a dc blocking capacitor is required on this pin. epad exposed pad. the e xposed pad must connect to rf/dc ground. table 6 . truth table control input signal path state a b rfc to low low rf1 high low rf2 low high rf3 high high rf4 interface schematics gnd 13714-005 figure 5 . gnd interface schematic v dd a/b 13714-006 figure 6 . logic control (a/b) interface schematic
data sheet HMC7992 rev. 0 | page 7 of 13 typical performance characte ristics insertion loss, isol ation, and return lo ss ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0 1 2 3 4 frequenc y (ghz) 5 6 7 8 insertion loss (db) +10 5 c +8 5 c +2 5 c ?4 0 c 13714-007 figure 7. insertion loss vs. frequency for various temperatures, v dd = 5 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 1 2 3 4 5 6 isol a tion (db) frequenc y (ghz) rfc t o rf2 rfc t o rf3 rfc t o rf4 13714-008 figure 8. isolation vs. frequency , v dd = 3.3 v to 5 v , rfc to rf1 = o n ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 1 2 3 4 5 6 isol a tion (db) frequenc y (ghz) rfc t o rf1 rfc t o rf2 rfc t o rf4 13714-009 figure 9. isolation vs. frequency, v dd = 3.3 v to 5 v, rfc to rf3 = o n ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0 1 2 3 4 5 6 7 8 insertion loss (db) frequenc y (ghz) 13714-010 +10 5 c +8 5 c +2 5 c ?4 0 c figure 10 . insertion loss vs. frequency for various temperatures, v dd = 3.3 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 1 2 3 4 5 6 isol a tion (db) frequenc y (ghz) rfc t o rf1 rfc t o rf3 rfc t o rf4 13714- 11 1 figure 11 . isolation vs. frequency, v dd = 3.3 v to 5 v, rfc to rf2 = o n ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 1 2 3 4 5 6 isol a tion (db) frequenc y (ghz) rfc t o rf1 rfc t o rf2 rfc t o rf3 13714- 1 12 figure 12 . isolation vs. frequency, v dd = 3.3 v to 5 v, rfc to rf4 = o n
HMC7992 data sheet rev. 0 | page 8 of 13 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 1 2 3 4 5 6 return loss (db) frequenc y (ghz) 13714- 1 13 figure 13 . return loss for rfc vs. frequency, v dd = 3.3 v to 5 v ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 1 2 3 4 5 6 return loss (db) frequenc y (ghz) rf1, rf2, rf3, and rf4 = on rf1, rf2, rf3, and rf4 = off 13714- 1 14 figure 14 . return loss for rf1, rf2, rf3, and rf4 vs. frequency, v dd = 3.3 v to 5 v
data sheet HMC7992 rev. 0 | page 9 of 13 input compression and input third-order intercept (0.1 ghz to 6.0 ghz) 26 28 30 32 34 36 38 40 0123456 input compression (dbm) frequency (ghz) +105c +85c +25c ?40c 13714-011 figure 15. input compression 1 db point vs. frequency for various temperatures, v dd = 5 v 26 28 30 32 34 36 38 40 0123456 input compression (dbm) frequency (ghz) +105c +85c +25c ?40c 13714-012 figure 16. input compression 0.1 db point vs. frequency for various temperatures, v dd = 5 v 45 50 55 60 65 0123456 iip3 (dbm) frequency (ghz) +105c +85c +25c ?40c 13714-013 figure 17. input third-order intercept (iip3) point vs. frequency for various temperatures, v dd = 5 v 26 28 30 32 34 36 38 40 0123456 input compression (dbm) frequency (ghz) +105c +85c +25c ?40c 13714-014 figure 18. input compression 1 db point vs. frequency for various temperatures, v dd = 3.3 v 26 28 30 32 34 36 38 40 0123456 input compression (dbm) frequency (ghz) +105c +85c +25c ?40c 13714-015 figure 19. input compression 0.1 db point vs. frequency for various temperatures, v dd = 3.3 v 45 50 55 60 65 0123456 iip3 (dbm) frequency (ghz) +105c +85c +25c ?40c 13714-016 figure 20. input third-order intercept (iip3) point vs. frequency for various temperatures, v dd = 3.3 v
HMC7992 data sheet rev. 0 | page 10 of 13 input compression an d input third - order intercept (10 k h z to 1 gh z ) input compression (dbm) frequenc y in log scale (mhz) 0.01 0.1 1 10 10 100 40 35 30 25 20 15 10 p1db p0.1db 13714-020 figure 21 . input compression (p 1db and p 0.1db points ) vs. frequency in log scale, v dd = 5 v at 25c 0.01 0.1 1 10 frequenc y in log scale (mhz) 10 100 65 60 55 50 45 40 35 30 25 iip3 (dbm) 13714-021 figure 22 . input third - order intercept ( i ip3) vs. frequency in log scale, v dd = 5 v at 25c
data sheet HMC7992 rev. 0 | page 11 of 13 theory of operation the HMC7992 requires a single positive supply voltage applied to the v dd pin. a b ypassing capacitor is recommended on the supply line to minimize rf coupling. the HMC7992 integrates with an internal 2:4 decoder ; the four rf paths are selected via the two digital control voltages applied to the a and b control inputs . a small value bypass ing capacitor is recommended on these digital signal lines to improve the rf signal isolation. the HMC7992 is internally matched to 50 ? at the rf c ommon port (rfc) and the rf ports (rf1, rf2, r f3 , and rf4); therefore, no external matching components are required. the rf pins are dc - coupled and dc blocking capacitors are required on the rf paths . the design is bidirectional; the rf input signals can apply at the rfc port or the rf1 to rf 4 ports . t he inputs and outputs are interchangeable. depending on the logic level applied to the control inpu t pins, a and b, one rf output port (for example, rf1) is set to on mode, by which an insertion loss path is provide d from the input to the output. the oth er rf output ports (for example, rf2, rf3 , and rf4) are then set to off mode, by which the outputs are isolated from the input. when the rf output ports (rf1, rf2, rf3 , and rf4) are in isolation mode, they are internally terminate d to 50 ?, and thereby can absorb the applied rf signal. the ideal power - up sequence is as follows: 1. power up gnd. 2. power up v dd . 3. p ower up the digital control inputs. the relative order of the logic control inputs is not important. powering the logic control inputs before the v dd s upply can inadvertently forward bias and damage the internal esd protection structures. 4. apply the rf input. t able 7 . switch mode operation digital control inputs signal mode a b rfc to rfx low low rf port 1 is in on mode , providing a low insertion loss path from the rfc port to the rf1 port. the remaining rf p orts (rf 2, rf 3, and rf 4) are in off mode; they are isolated from the rfc port and internally terminated to a 50 ? load. high low rf port 2 is in on mode , providing a low insertion loss path from the rfc port to the rf2 port. the remaining rf p orts (rf 1, rf 3, and rf 4) are in off mode; they are isolated from the rfc port and internally terminated to a 50 ? load. low high rf port 3 is in on mode , providing a low insertion loss path from the rfc port to the rf3 port. the remaining rf p orts (rf 1, rf 2, and rf 4) are in off mode; they are isolated from the rfc port and internally terminated to a 50 ? load. high high rf port 4 is in on mode , providing a low insertion loss path from the rfc port to the rf4 port. the remaining rf p orts (rf 1, rf 2, and rf 3) are in off mode; they are isolated from the rfc port and internally terminated to a 50 ? load.
HMC7992 data sheet rev. 0 | page 12 of 13 applications information generate the evaluation pcb with proper rf circuit design techniques. signal lines at the rf port must have a 50 impedance, and the package ground leads and backside ground slug must connect directly to the ground plane, as shown in figure 23. the evaluation board shown in figure 23 is available from analog devices, inc., upon request. table 8. bill of materials for the ev1HMC7992lp3d 1 evaluation board reference designator description j1 to j5 pcb mount sma connectors c1 to c5 100 pf capacitors, 0402 package c8 to c10 100 pf capacitors, 0402 package c13 0.1 f capacitor, 0402 package r1 to r2 0 resistors, 0402 package u1 HMC7992lp3de sp4t switch pcb 2 600-01284-00 evaluation pcb 1 reference this evaluation board number when ordering the complete evaluation board. 2 circuit board material: roger 4350 or arlon 25fr. 13714-017 figure 23. e v1HMC7992lp3d evaluation board
data sheet HMC7992 rev. 0 | page 13 of 13 outline dimensions 3.10 3.00 sq 2.90 0.30 0.25 0.20 1.92 1.70 sq 1.48 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r * 0.35 0.30 0.25 seating plane 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 0.95 0.85 0.75 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 01-08-2015-a pkg-000000 * compliant with jedec standards mo-220-veed-4 with the exception of package edge to lead edge. figure 24. 16-lead lead frame chip scale package [lfcsp] 3 mm 3 mm body and 0.85 mm package height (cp-16-38) dimensions shown in millimeters ordering guide model 1 temperature range msl rating 2 package description package option branding 3 HMC7992lp3de C40c to +105c msl3 16-lead lead frame chip scale package [lfcsp] cp-16-38 xxxx 7992 HMC7992lp3detr C40c to +105c msl3 16-lead lead frame chip scale package [lfcsp] cp-16-38 xxxx 7992 ev1HMC7992lp3d evaluation board 1 the HMC7992lp3de and HMC7992lp3de tr are rohs compliant parts. 2 see the absolute maximum ratings se ction for msl rati ng information. 3 4-digit lot number xxxx. ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d13714-0-1/16(0)

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